This invention relates to logic circuits. More particularly, it is concerned with logic circuits employing complementary transistors.
Basic logic gates are used extensively in logic circuit design to implement the Boolean Algebra of either combination logic or sequential circuits. Basic logic circuits frequently employ complementary metal-oxide-semiconductor (CMOS) transistors. One widely-used logic gate circuit is the so-called NAND-gate. With previously known CMOS NAND-gates the speed of switching between operating states increases with the number of inputs to the gate. This gate delay becomes significant when the number of inputs to the gate is greater than five. For instance, when a NAND-gate is used as a decoding element of the control section in high speed signal processing and high speed switching applications, the gate delay will affect the entire system throughput becoming a dominant factor in determining the system performance.
One approach for improving the speed-degrading problem of gate delay is to separate the NAND-gate into several NAND-gates, each having only a few inputs, and connecting the outputs of the several NAND-gates to an OR-gate. Such an arrangement, however, increases the number of stages of delay from one to three; the NAND-gates, a NOR-gate, and an inverter. Another approach is to increase the size of the MOS transistors in order to increase both the charging and the discharging speeds at the output of the gate. Increasing the size of a transistor beyond a certain amount, however, increases the source-drain and the gate capacitances of the transistor thus degrading the charging and discharging speed.